1. Technical Field
The invention relates to a plasma reactor having parallel plates for interposition therebetween of a workpiece to be processed, such as a semiconductor wafer, and an inductive coil antenna coupling RF power through one of the parallel plates into the interior of the reactor.
2. Background Art
(1) Background Relating to the Reactor Apparatus
Inductively coupled plasma reactors for processing microelectronic semiconductor wafers, such as the type of reactor disclosed in U.S. Pat. No. 4,948,458 to Ogle, enjoy important advantages over parallel-plate capacitively coupled plasma reactors. For example, inductively coupled plasma reactors achieve higher plasma ion densities (e.g., on the order of 1011 ions/cm3). Moreover, plasma ion density and plasma ion energy can be independently controlled in an inductively coupled plasma reactor by applying bias power to the workpiece or wafer. In contrast, capacitively coupled reactors typically provide relatively lower plasma ion densities (e.g., on the order of only 1010 ions/cm3) and generally cannot provide independent control of ion density and ion energy. The superior ion-to-neutral density ratio provided by an inductively coupled plasma etch reactor used to etch silicon dioxide, for example, provides superior performance at small etch geometries (e.g., below 0.5 micron feature size) including better etch anisotropy, etch profile and etch selectivity. In contrast, parallel plate capacitively coupled plasma reactors typically stop etching at feature sizes on the order of about 0.25 microns, or at least exhibit inferior etch selectivity and etch profile due to an inferior ion-to-neutral density ratio.
One type of inductively coupled plasma reactor, such as one disclosed in U.S. Pat. No. 4,948,458, has a planar coil overlying the chamber ceiling and facing the semiconductor wafer being processed, which provides a relatively uniform RF induction field over the surface of the wafer. For this purpose, the ceiling, which seals the reactor chamber so that it can be evacuated, must be fairly transmissive to the RF induction field from the coil and is therefore a dielectric, such as quartz. It should be noted here that such a ceiling could be made from dielectric materials other than quartz, such as aluminum oxide. However other materials such as aluminum oxide tend produce greater contamination than quartz due to sputtering.
An advantage of capacitively coupled plasma reactors is that the chamber volume can be greatly reduced by reducing the space between the parallel plate electrodes, thereby better confining or concentrating the plasma over the workpiece, while the reactor can be operated at relatively high chamber pressure (e.g., 200 mTorr). In contrast, inductively coupled plasma reactors require a larger volume due to the large skin depth of the RF induction field, and must be operated at a lower chamber pressure (e.g., 10 mTorr) to avoid loss of plasma ions due to recombination. In commercial embodiments of the inductively coupled reactor of U.S. Pat. No. 4,948,458 referred to above, the requirement of a large chamber volume is met by a fairly large area side wall. Typically the ceiling must be a non-conductive material in order to permit inductive coupling from the overhead coil antenna into the chamber interior, and is therefore not available to provide an RF ground or RF return plane. Therefore, the chamber side walls must provide the RF ground or RF return and must therefore be formed of a conductive material such as aluminum, for example. However, the side wall is a poor ground plane, as it has many discontinuities, such as a slit valve for wafer ingress and egress, gas distribution ports or apparatus and so forth. Such discontinuities give rise to non-uniform current distribution, which distort plasma ion distribution relative to the wafer surface. The resulting sideways current flow toward the side wall contributes to non-uniform plasma ion distribution relative to the wafer surface.
One approach for combining capacitive and inductive coupling is to provide a side coil wound around the side wall of a parallel plate plasma reactor, as disclosed in European Patent Document Publication No. 0 520 519 A1 by Collins et al. For this purpose, the cylindrical chamber side wall must be a nonconductor such as quartz in order to admit the RF induction field of the side coil into the chamber. This type of plasma reactor may tend to exhibit, under certain circumstances, processing non-uniformity across the wafer surface. For example, the etch rate is much greater at the wafer periphery and much slower at the wafer center, thereby constricting the process window. The disposition of the induction coil antenna along the side wall of the reactor chamber, the relatively short (e.g., 2 cm) skin depth (or depth within which most of the RF power is absorbed) toward the chamber center, and the introduction of the etch precursor gas into the reactor chamber from the side, tends to provide more of the etchant ions and radicals near the chamber side wall or around the wafer periphery. The phrase xe2x80x9cetchant ions and radicalsxe2x80x9d as employed in this specification refers to the various chemical species that perform the etch reaction, including fluorocarbon ions and radicals as well as fluoro-hydrocarbon ions and radicals. The population of free fluorine ions and radicals is preferably minimized by well-known techniques if a selective etch process is desired. Energetic electrons generated by the plasma source power interact with the process precursor gas and thereby produce the required etchant ions and radicals and, furthermore, produce molecular or atomic carbon necessary for polymerization employed in sophisticated etch processes. The etch process near the wafer center is dependent upon such energetic electrons traveling from the vicinity of the chamber side wall and reaching the wafer center before recombining along the way by collisions with neutral species or ions, so that the etch process is less uniform across the wafer surface. These problems are better understood in light of the role polymerization plays in the etch process.
Polymerization employing fluoro-carbon (CXFX) or fluoro-hydrocarbon chemistry is employed in a typical silicon dioxide etch process, for example, to enhance etch anisotropy or profile and etch selectivity, as described in Bariya et al., xe2x80x9cA Surface Kinetic Model for Plasma Polymerization with Application to Plasma Etching,xe2x80x9d Journal of the Electrochemical Society, Volume 137, No. 8 (August 1990), pp. 2575-2581 at page 1. An etch precursor gas such as a fluoro-carbon like C2F6 or a fluoro-hydrocarbon introduced into the reactor chamber dissociates by inelastic collisions with energetic electrons in the plasma into etchant ions and radicals as well as carbon. As noted above, such etchant ions and radicals include fluoro-carbon or fluoro-hydrocarbon ions and radicals, for example, and free fluorine ions and radicals. The free fluorine ions and radicals are preferably minimized through scavenging, for example, if the etch process is to be selective with respect to a non-oxygen containing material such as polysilicon. The carbon and at least some of the fluoro-carbon or fluoro-hydrocarbon ions and radicals are polymer-forming. Also present in the plasma are excited neutrals or undissociated species and etch by-products. The polymer-forming radicals and carbon enhance etch profile as follows: By forming only on the side-walls of etch features (formation on the horizontal surfaces being prevented by the energetic downward ion flux from the plasma), polymers can block lateral etching and thereby produce anisotropic (narrow and deep) profiles. The polymer-forming ions and radicals also enhance silicon oxide etch selectivity because polymer generally does not form on the silicon oxide under favorable conditions but does form on silicon or other materials which are not to be etched but which may underlie a silicon oxide layer being etched. Thus, as soon as an overlying silicon oxide layer has completely etched through to expose an underlying polysilicon layer, the polymer-forming ions and radicals in the plasma that contact the exposed polysilicon layer immediately begin to form a polymer layer, inhibiting further etching.
Such polymerization during the etch process requires a careful balance of etchant and polymer, the etchant concentration typically being at a depletion level to avoid inhibition of appropriate polymer formation. As a result, a significant proportion of etchant ions and radicals formed near the wafer periphery are consumed before reaching the wafer center, further depleting the etch ion concentration over the wafer center. This leads to a lower etch rate or etch stopping near the wafer center.
One reason that there are more ions at the wafer periphery is that the location of the inductive coil at the side wall causes hotter ion-producing electrons to be generated in the vicinity of the side wall, such electrons cooling off and/or being consumed by recombination before reaching the center so that less production of etchant ions and radicals occurs over the wafer center. Moreover, introduction of the etchant precursor gas from the side and coupling of plasma source power from the side tends to produce a less uniform etchant ion/radical distribution favoring the side. Many of the ions and radicals formed near side (over the wafer periphery) are consumed by etching the quartz side wall and are not available to etch the wafer center, while etchant ion/radical-forming energetic electrons generated near the side are lost to collisions with other species before reaching the wafer center, thus reducing the etchant ion concentration at the wafer center. (It should be noted that the etching of the quartz side wall eventually increases the cost of operating the reactor.) The relative lack of etchant ions near the wafer center permits faster formation of polymer at the wafer center, and in some cases the polymer formation can inhibit the etch process, particularly at feature sizes less than 0.5 microns. Such etch stopping may occur either at larger etch features, at shallower etch depths or at shorter etch times.
The converse of the foregoing is that the relative plentitude of etchant ions and radicals near the wafer periphery can, under selected processing conditions, so impede polymerization as to impair etch selectivity, possibly leading to punchthrough of the underlying layer near the wafer periphery, in addition to causing a much higher etch rate at the wafer periphery. A related problem is that the hotter electrons near the chamber side wall/wafer periphery providing more energetic plasma ions in that vicinity, coupled with the oxygen released by the etching of the quartz side wall mentioned above, erode the edges of the photoresist mask near the wafer periphery. Such erosion may lead to faceting, in which the corners defined by the photoresist mask are etched, giving rise to an undesirable tapered etch profile.
From the foregoing, it is clear that there is a trade-off between avoiding punchthrough and faceting at the wafer edge and avoiding etch stopping at the wafer center, leading to a relatively narrow window of processing parameters within which a successful etch process may be realized across the entire wafer surface. To avoid the overetching the wafer periphery, the concentration of etchant ions and radicals in the plasma relative to other particles (e.g., polymer-forming ions or radicals and carbon) may be decreased, which risks etch-stopping at the wafer center. Conversely, to avoid etch-stopping at the wafer center, the concentration of etchant ions in the plasma may be increased, which risks punch through or faceting near the wafer periphery. Thus, the process window for successfully etching the entire wafer is relatively narrow.
In the parallel plate plasma reactor, the concentration of free fluorine in the plasma can be controlled by introducing a scavenging article, such as silicon, near or at the top of the reactor chamber. Silicon atoms physically etched (sputtered), chemically etched or reactive ion etched from the scavenging article combine with the fluorine ions and radicals, thereby reducing fluorine ion and radical concentration in the plasma. By controlling the rate at which silicon atoms are physically or chemically etched from the scavenging article, the amount of free fluorine ions and radicals in the plasma may be regulated (e.g., reduced) as desired to meet the narrow processing window mentioned above. The physical or chemical etch rates can be controlled by controlling the temperature of the scavenging article and/or by controlling the rate of ion-bombardment on the scavenging article. The surface of the scavenging article may be activated (to release silicon atoms into the plasma) either by RF power or by heating. By holding the scavenging article""s temperature below the temperature at which polymerization occurs, the polymers accumulate on the scavenging article surface and block any release therefrom of silicon atoms. By raising the scavenging article""s temperature above the condensation temperature, the surface is free from polymers, thus permitting the release of silicon atoms into the plasma. Further increasing the temperature increases the rate at which silicon atoms are released from the scavenging surface into the plasma. As for activating the scavenging article by RF power, the rate of ion bombardment of the scavenging article is affected by the RF potential or bias applied (directly or indirectly) to the top parallel plate electrode adjacent the scavenging article. Reducing the free fluorine concentration in this manner has the effect of not only decreasing etch rate but also enriching the carbon content of the polymer, thus increasing the effect of the polymer on the etch process to guard against punch through at the wafer periphery, but increasing the risk of etch stopping at the wafer center. Conversely, increasing the free fluorine concentration not only increases the etch rate but also depletes the carbon content of the polymer, thus decreasing the effect of polymerization on the etch process, thus decreasing the risk of etch stopping at the wafer center but weakening the protection against punch through at the wafer periphery.
The narrow processing window is also met by regulating the polymer-forming ion and radical concentration in the plasma. This is accomplished by regulating the rate at which such polymer-forming radicals and ions are lost from the plasma by polymerization onto the chamber ceiling or sidewalls (or a scavenging article) or the rate at which polymer deposits are sputtered from the ceiling or sidewalls (or scavenging article). The polymerization rate at the ceiling is affected by regulating the ceiling temperature above or below the polymerization temperature. The rate at which such polymer deposits on the ceiling are etched and released into the plasma is affected by the following factors: the RF power applied (directly or indirectly) to the ceiling electrode, temperature, chamber pressure, gas flow rate, inductive source power and other parameters.
Thus, in order to meet the narrow processing window, in general the relative concentrations of free fluorine and polymer-forming ions and radicals in the plasma may be controlled by regulating the temperature of the chamber ceiling or side walls or a scavenging article (if any) and/or by regulating the RF power applied to the to overhead/ceiling parallel plate electrode.
Thus, it is seen that the parallel-plate plasma reactor with the induction coil wound around its cylindrical-side wall has the advantage of providing its ceiling electrode as a uniform ground plane over the entire wafer surface, but confines plasma ion production to the vicinity of the chamber side wall, so that plasma processing is weaker at the wafer center and stronger at the wafer periphery. The overhead planar coil plasma reactor has the advantage of a more uniform RF induction field relative to the wafer surface, so that ion production is not confined to the wafer periphery, but suffers from the lack of any uniform ground plane over the wafer, so that plasma ion current flow to the side walls distorts the plasma.
In a typical plasma processing chamber used for selective etching of thin films on a semiconductor wafer, a combination of etch and deposition processes are employed simultaneously. Polymer forms on surfaces that are either sufficiently cold (below the temperature threshold of polymerization) or on which ion bombardment is below a threshold energy (the threshold ion energy sufficient to offset the polymer deposition rate on that surface). The temperature threshold and the threshold ion energy depend upon the material of the surface. Deposition can occur on the wafer as well as the process chamber surfaces. Control of the deposition on the wafer as well as the process chamber surfaces is critical to controlling the selective etch process. Polymer deposition on interior surfaces of reactor chamber walls is required in cases where the material of the chamber walls is incompatible with the process being carried out on the wafer. One example of this is where the chamber walls are aluminum and the process being carried out is plasma etching of silicon dioxide. Deposition of polymer on the chamber wall surfaces prevents introduction of aluminum into the process by preventing plasma ion sputtering of the chamber walls.
Conventional techniques for controlling polymer deposition required the user to choose between the following two options:
(1) Keeping the process chamber surfaces below the threshold temperature or keeping the ion energy below the threshold ion energy in order to cause polymer deposition on the surfaces;
(2) Keeping process chamber surfaces above the threshold temperature or keeping the ion energy above the threshold ion energy in order to prevent polymer deposition on the surfaces.
The problem with option (1) is that the polymer accumulated on the surface must be removed periodically, either by manual (wet) cleaning, by plasma (dry) cleaning, or by replacing the contaminated parts. Otherwise, flaking of the polymer will occur, leading to contamination of the chamber. Cleaning the reactor chamber requires the reactor operation be interrupted during the entire cleaning process, which represents a significant loss of productivity and increases the cost of operating the reactor. Problems associated with the plasma cleaning process include not only loss of productivity but also loss of consumable materials in the chamber and contamination.
The problem with option (2) is that etching of chamber surfaces occurs because the surfaces are exposed. Typically, these surfaces are either aluminum or quartz. For aluminum surfaces, etching creates contaminant by-products that can destroy the integrity of the plasma processing of the wafer, as mentioned hereinabove. For quartz surfaces, the etching can occur at such a high rate that the quartz parts must be replaced periodically at a significant cost in parts and lost production time. Moreover, some transition to colder surfacesxe2x80x94in other regions of the chamber such as the pumping annulusxe2x80x94must be provided.
(2) Background Relating to the Present Invention
The etch process becomes more difficult to carry out as new device geometries are introduced requiring greater versatility of the etch process. The apparatus described in this specification has successfully performed at relatively high plasma ion densities on the order of 1011 ions/cm3 and greater. However, some semiconductor structures need to be etched at lesser plasma densities, e.g., on the order of 5xc2x71010 ions/cm3. The following are some examples of such structures.
(1) Self-Aligned Contact (SAC): A self-aligned contact in a multi-level conductor structure is one in which a portion of the opening to be etched is near a lower-level bit line or conductor adjacent the bottom of the opening, for example. Normally, the contact opening location must be carefully controlled during photolithographic definition to avoid exposing the bit line to the metal deposited into the etched opening. However, depending upon the dimensions involved, the photolithographic definition process may not be a sufficiently reliable guarantee of accurate placement of the contact opening to avoid exposing the lower-level bit line. In order to ensure the insulation of the lower-level bit line from the metal deposited inside the contact opening even in the presence of significant placement errors in the photolithographic definition step, a silicon nitride film is formed around the lower level bit line before formation of the overlying layers through which the contact opening is to be etched. The challenge is to avoid etching through the silicon nitride cover layer without etch-stopping above the desired depth of the contact opening. This challenge is particularly difficult for two reasons: (a) First, if the contact opening partially overlies the lower-level bit line, it is constricted by the lower-level bit line, thereby increasing the likelihood of etch-stopping. (b) Second, the silicon nitride insulating film covering the lower-level bit line tends to have an outer corner facing the contact opening, which is highly susceptible to sputtering, thereby increasing the likelihood of damaging or etching through the silicon nitride insulating film.
(2) Self-Aligned Local Interconnect (SALI): In a self-aligned local interconnect structure, contact openings are etched at the same time large-area openings are etched, whose width may be an order of magnitude or more greater than the width of a typical contact opening. It is very difficult to maintain adequate etch selectivity in the large-area openings without etch-stopping in the contact (narrow) openings.
(3) Dual Damascene: A narrow contact opening is formed at the bottom of a large-area trench, both the trench and the contact being etched in the same etch step. In this structure, it is especially difficult to avoid exceeding the critical opening dimensions of the overhead trench without etch-stopping in the underlying contact opening, for the following reasons:
(a) the disparity in opening sizes between the trench and contact;
(b) the use of special low-dielectric constant material instead of or as an additive within the silicon oxide insulating layers renders these layers less susceptible to attack by the enchant, and therefore reduces etch selectivity;
(c) the underlying stop layer (e.g., polysilicon or silicon) contains oxide additives which renders this layer more susceptible to attack by the enchant, and therefore reduces etch selectivity.
As already mentioned, carrying out these latter applications using the reactor described in this specification has been difficult for the reasons outlined immediately above. It is believed that other types of inductively coupled plasma reactors can experience similar difficulties.
One approach to such handling problems has been to simply decrease the plasma source power from its typical level corresponding to a plasma density of over 3xc2x71011 ions/cm3 to reduce the plasma density. However, the problem with this approach is that, as the plasma source power is reduced, the skin depth of the inductive field in the plasma expands until, at or below 3xc2x71011 ions/cm3, the skin depth reaches the lower limit (i.e., the level of the wafer or workpiece), at which point inductive coupling ceases and the plasma abruptly switches over to a purely capacitively coupled mode and a much lower plasma ion density of about 1xc2x71010 ions/cm3. In the capacitively coupled mode it is not possible to achieve a higher plasma density, so that it would appear that it is not possible to operate the above-described reactor (or other inductively coupled reactors) at an intermediate plasma density (e.g., 5xc2x71010 ions/cm3, which would be more desireable. In addition, in the capacitively coupled mode there is no independent control of plasma ion density and plasma ion energy at the wafer surface, resulting in inadequate plasma density and excessive ion energy. Such excessive ion energy increases the risk of punching through the silicon nitride insulating layer exposed during contact etching, for example. The inadequate plasma ion density reduces process throughput or productivity. Thus, one problem is how to obtain an intermediate plasma ion density while maintaining inductive coupling of the RF source power.
The present invention is embodied in a method of operating an inductively coupled plasma reactor for processing a semiconductor wafer, the reactor including a vacuum chamber for containing the wafer, a process gas source, a semiconductor window electrode facing an interior portion of the chamber, an inductive power radiator on an exterior side of the semiconductor window electrode, the inductive field having a skin depth generally decreasing with the frequency of the RF inductive field and with the density of the plasma in the chamber and generally increasing with the pressure inside the vacuum chamber, the inductive coupling of the RF field tending to approach extinguishment as the skin depth approaches the spacing between the wafer and the window electrode, a method for maintaining an intermediate plasma density inside the chamber without extinguishing the inductive coupling of the RF field, the method including operating the reactor at a selected flow rate of the process gas, a selected chamber pressure and a selected plasma source power level corresponding to the reduced plasma density, and maintaining the frequency of the RF field at a level sufficient to reduce the skin depth to a depth less than the electrode-to-wafer spacing, whereby to maintain the inductive coupling of the RF field.
The electrode-to-wafer spacing is typically on the order of about 7 cm. The high plasma density is typically between about 1xc2x71011 electrons/cm3 to 10xc2x71011 electrons/cm3 and the intermediate plasma density is between about 1xc2x71010 electrons/cm3 to 10xc2x71010 electrons/cm3. Typically the frequencies in the invention exceed by a factor of between 4 and 100 the typical frequency of operation of inductively coupled plasma reactors. The typical (low) frequency of operation is on the order of about 2 MHz; while, in contrast, the frequency employed in the present invention is on the order of about 13 MHz. Alternatively, the source power frequency employed in the present invention may be within a range between about 13 and 100 MHz. The chamber pressure typically lies in a range between on the order of about 2 mTorr and 100 mTorr or, alternatively between on the order of about 2 mTorr and 200 mTorr. The chamber pressure may lie in a range of between about 25 to 100 mTorr. Alternatively, the chamber pressure is in a range of between about 40 and 100 mTorr. As a second alternative, the chamber pressure is in a range of between about 2 and 25 mTorr. As a third alternative, the chamber pressure is in a range of between about 2 and 40 mTorr. The intermediate plasma density is within about one order of magnitude of a high plasma density. The electrode-to-wafer spacing is typically a fraction of the diameter of the wafer.
In accordance with an additional feature of the invention, the method further includes an RF bias power generator for applying plasma bias power to the wafer, the method further including maintaining the frequency of the RF bias power generator at least at a level sufficient to limit ion energies near the wafer below a desired threshold, such as, for example, about 2 KeV peak ion energy. For example, the RF bias power frequency is maintained above 10 MHz to achieve keep ion energy at the wafer surface below a threshold of about 2 KeV.